With regards to auxiliary equipments with high field-effect mobility requirements in a-Si and poly-Si TFT applications, such as a video scanner, the poly-Si TFT has a significant advantage.
The traditional poly-Si TFT inherently has relatively larger crystal particles and therefore has a relatively higher electron mobility. However, when the circuit is cut-off, there is also a relatively higher amount of electric current leakage, and the electric current leakage of poly-Si TFT relative to that a-Si TFT has already exceeded the acceptable limit for applications with LCD (Liquid Crystal Display) products.
Investigations have shown that the reasons for the electric current leakage in low-temperature poly-Si TFT structures can be attributed to defects in the particle boundaries and the hole current that is generated at the high electric field near the drain. Therefore, reducing the defects in the particle boundaries and lowering the high electric field near the drain would be able to achieve the objective of controlling the electric current leakage.
Currently, the known techniques for solving the aforesaid problem include: (1) offset gate structure, (2) lightly dopant drain or LDD structure, and (3) stack source/drain structure). Examples have been introduced in the articles by Po-Sheng Shih et al., (“A novel lightly doped drain polysilicon thin-film transistor with oxide sidewall spacer formed by one-step selective liquid phase deposition”, IEEE Electron Device Letters, vol. 20, pp. 421-423, August 1999) and Kenji Sera et al., (“High-Performance TFTs Fabricated by XeCl Ecimer Laser Annealing of Hydrogenated Amorphous-Silicon Film”, IEEE Electron Device Letters, vol. 36, no. 12, pp. 2868-2872, December 1989). These methods to lower the high electric current leakage in poly-Si TFT structures are able to increase the on/off current ratio. However, with regards to offset gate and LDD structures, due to the fact that the aforesaid methods involve an extra step of ion implantation, the components easily suffer collisions with high-energy ions during the ion implantation, thus causing the drain to suffer damage. This phenomenon has been disclosed in an article by Kwon-Young Choi and ors (“A novel gate-overlapped LDD poly-Si thin film transistor,” IEEE Electron Device Letters, vol. 17, pp. 566-568, December 1996). In particular, such damage is irreversible in the case of low-temperature poly-Si TFT structures where the temperature is subject to restraints during production.
In the method by Kenji Sera et al. that is described above, a stagger source/drain TFT structure can be used, as shown in FIG. 1, and defined based on the number of times that the reticle is used, and there are at least 5 steps in the process, including (1) first, two independent poly-Si (02) islands are defined, and a thick staggered source/drain structure is formed on a thermal oxide (01) substrate by depositing a poly-Si (02) layer and coating photoresistor (03) and then exposed and then etched; (2) deposit the poly-Si TFT (02′), followed by coating the photoresistor (03) again, and then exposing it and etching it to form a poly-Si (02) channel region; (3) defining the gate of poly-Si and deposit the gate oxide (04) film and poly-Si TFT (02″), followed by coating the photoresistor (03) again and then exposing and etching; (4) define the metal conductor line (10) contact window (14) region; and (5) defining the metal conductor line (10) region at the external connection for the component.
Although it is known that the method by Kenji Sera et al. is able to achieve a relatively good electric performance, when compared with the standard four mask steps for traditional co-plannar components, there is now an extra step and thereby makes the process more complicated. Besides the production costs, the extra step in the process also increases the errors when switching between images. It is therefore not suitable for mass production of TFT-LCD products.